SoC Architect

Join our cutting-edge startup adventure!

Who are we?
Imagine being part of the dynamic journey at Qualinx – a startup born when three visionary PhD Engineers from TU Delft set out to revolutionize radio chip technology. At Qualinx, we're on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. With a great team of over 40 individuals, scaling to 60 next year, hosting more than 17 nationalities, we've achieved the impossible - the world's lowest power GNSS chipset. Now, we're on the verge of unleashing our game-changing digital RF technology product, ready to flood the market with millions of annual shipments.

What Sets Us Apart

Joining Qualinx isn't just about a job; it's about embracing high standards, and boldly navigating unexpected challenges. We thrive on collaboration, with a commitment to self-improvement and product excellence. At Qualinx, you're not just an employee; you're an integral part of our exciting journey, contributing to the growth and success of a groundbreaking solution.

Key Responsibilities

• System Design & Integration: You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip.
• You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
• You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
• You will define and implement security features to protect the SoC from vulnerabilities.
• You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
• Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Requirements

Qualinx is looking for a result-driven and conscientious senior SoC Architect. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated. The ideal candidate for this role must have:

• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse).
• Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
• Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
• Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g., SPI, I2C, UART).
• Expertise in analog-digital interface design, including mixed-signal circuits, ADC/DAC integration, and layout constraints for minimizing noise and signal interference.
• Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
• Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
• Hands-on experience with IP selection to meet the specific needs of the design.
• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
• Strong knowledge of pad ring placement and ESD strategy.
• In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
• Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
• Solid Knowledge in signal processing, communication system.
• Strong knowledge in all aspects of RFIC system design.